Integrated circuits are an integral part of any electronic device. A variety of integrated circuits are often used together to enable the operation of the electronic device. While integrated circuits are typically designed for a particular application, one type of integrated circuit which enables flexibility is a programmable logic device (PLD). A programmable logic device is designed to be user-programmable so that users may implement logic designs of their choices. One type of programmable logic device is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” having a two-level AND/OR structure connected together and to input/output (I/O) resources by an interconnect switch matrix. Another type of programmable logic device is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
However, programmable logic devices are typically relatively complex and have physically large dice. In implementing semiconductor devices, it is important that the devices are free of defects and reliable throughout their use. When a semiconductor device fails after being installed in a device such as a consumer electronics device, such a failure may cause the entire consumer electronics device to fail. The large die size means that fewer dice are produced per wafer. Further, the chances that a physical defect, such as a dust particle on any portion of a die, may cause an electrical fault is increased. The minimum critical dimensions and number of layers of programmable logic devices also increase the possibility for electrical faults. Accordingly, programmable logic devices are tested after fabrication, and are binned according to performance, such as operating speed, as well as for pass/fail. The percentage of usable dice is called “silicon yield” because it indicates the fraction of usable integrated circuits in a manufactured lot. Since the device is larger and the logic is denser, there is a greater probability that the device will have a fatal defect. Because the number of usable dice significantly impacts profitability, it is important to enable the use of as many of the die of the wafer as possible.
One way to enable the use of defective programmable logic devices is to avoid the use of defective logic. However, customers are generally not able to specify their board timing well enough to enable PLD design tools to ensure that the programmable logic device will meet the timing requirements of the board. Therefore, the board must be qualified. Because the timing of paths in different implementations will be different, a quality-conscious customer may need to verify proper functionality of every possible bitstream in the system. If there are sixteen different possible bitstreams, the customer must qualify sixteen different systems. This qualification process may be expensive. Further, if the customer has two programmable logic devices in the system, he may need to qualify all combinations of the two programmable logic devices implementing the 16 designs, or 256 different systems. Testing that many systems would be too expensive and time consuming for nearly all customers.
While users of programmable logic devices have design constraints, and configuration tools typically meet all design constraints, there are some nets or paths that the customer does not constrain. This is typically because these nets or paths may not be enough of a concern for a customer to go to the effort of constraining them. In an implementation using conventional design tools, these unconstrained nets or paths are assigned whatever timing the tools provide, which can be very long. If timing is not an issue, then there is no problem with the unconstrained nets or paths. However, there may be timing issues with some of the unconstrained nets or paths. There is a further problem in that conventional tools may take a timing-constrained path and have it barely meet the timing in one design, but have a very large slack in another. That is, the constrained paths may have large variation, making it difficult to validate (qualify) a programmable logic device having a given design on a system.
Accordingly, there is a need for an improved method of implementing a programmable logic device adapted to receive one of a plurality of configuration bitstreams for a circuit design. There is a further need for an improved method for generating multiple implementations to avoid defects. One or more of these methods may simplify the validation process for the configuration bitstreams in the programmable logic device.